
module frv_soc_top #(
    parameter UDIV = 868

)(
    input               clk             ,
    input               rst_n           ,
    // Program Downloader Interface
    // input               pd_rx           ,
    // output              pd_tx           ,
    // UART Interface
    input               uart0_rx        ,
    output              uart0_tx        ,
    // input               uart1_rx        ,
    // output              uart1_tx        ,
    // SWTICH BUTTON and typed Button
    input [15:0]        swc_vec         ,
    input [4:0]         btn_vec         ,
    output [8-1:0] 		seg             ,
	output [4-1:0] 		dig             
    // PWM SIG
    // output              pwm_sig         
);

wire                      pd_rst          ;
wire                      pd_wr           ;
wire[31:0]                pd_wdata        ;
wire[8:0]      pd_waddr        ;
wire                      plic_int_vld    ;
wire                      clic_int_vld    ;

wire                      sys_clk         ;

assign sys_clk = clk;

Axi4LiteIf  axi_core(sys_clk);
Axi4LiteIf  axi_devices[8](sys_clk);

assign axi_core.rst_n = rst_n;
assign axi_devices[0].rst_n = rst_n;
assign axi_devices[1].rst_n = rst_n;
assign axi_devices[2].rst_n = rst_n;
assign axi_devices[3].rst_n = rst_n;
assign axi_devices[4].rst_n = rst_n;
assign axi_devices[5].rst_n = rst_n;
assign axi_devices[6].rst_n = rst_n;
assign axi_devices[7].rst_n = rst_n;

assign pd_rst          = 0 ;
assign pd_wr           = 0 ;
assign pd_wdata        = 0 ;
assign pd_waddr        = 0 ;
assign plic_int_vld    = 0 ;
assign clic_int_vld    = 0 ;


axi_frv_core_wrapper _axi_frv_core_wrapper(
    .pd_rst          (pd_rst      ),
    .pd_wr           (pd_wr       ),
    .pd_wdata        (pd_wdata    ),
    .pd_waddr        (pd_waddr    ),
    .plic_int_vld    (plic_int_vld),
    .clic_int_vld    (clic_int_vld),  
    .master          (axi_core    )
);

axi_crossbar_wapper crossbar(
    .slave                  (axi_core),
    .masters                (axi_devices)
);

axi_uart_ctrl #(
    .AW(32),
    .BR_DIV(UDIV) //20_000_000/115200=173
)_axi_uart_ctrl (
.rxd     (uart0_rx  ),
.txd     (uart0_tx  ),
.slave   (axi_devices[0])
);

axi_btn_ctrl _axi_btn_ctrl (
.switch_in      (swc_vec),
.button_in      (btn_vec),	//u d l r c
.slave          (axi_devices[1])  
);

axi_dig_disp_dev _axi_dig_disp_dev(
.seg    (seg),
.dig    (dig),
.slave  (axi_devices[7])
);

// soc_pll soc_pll_inst(
// // Clock out ports
// .clk_out1(sys_clk),     // output clk_out1
// // Status and control signals
// .reset(~rst_n), // input reset
// .locked(),       // output locked
// // Clock in ports
// .clk_in1(clk));      // input clk_in1


endmodule



